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00041 !DATE
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00049
00051 #ifndef _NVAPI_H
00052 #define _NVAPI_H
00053
00054 #pragma pack(push,8) // Make sure we have consistent structure packings
00055
00056 #ifdef __cplusplus
00057 extern "C" {
00058 #endif
00059
00060
00061
00062
00063 #ifndef _WIN32
00064 #define __cdecl
00065 #endif
00066
00067 #define NVAPI_INTERFACE extern NvAPI_Status __cdecl
00068
00069 #if defined(__GNUC__) || defined(__arm) || defined(__IAR_SYSTEMS_ICC__) || defined(__ghs__) || defined(_WIN64)
00070 typedef unsigned long long NvU64;
00071 #else
00072 typedef unsigned __int64 NvU64;
00073 #endif
00074
00075
00076 #if (defined(macintosh) || defined(__APPLE__)) && !defined(__LP64__)
00077 typedef signed long NvS32;
00078 #else
00079 typedef signed int NvS32;
00080 #endif
00081
00082 typedef unsigned long NvU32;
00083 typedef unsigned short NvU16;
00084 typedef unsigned char NvU8;
00085
00086 #define NV_DECLARE_HANDLE(name) struct name##__ { int unused; }; typedef struct name##__ *name
00087
00097 NV_DECLARE_HANDLE(NvDisplayHandle);
00098 NV_DECLARE_HANDLE(NvUnAttachedDisplayHandle);
00099 NV_DECLARE_HANDLE(NvLogicalGpuHandle);
00100 NV_DECLARE_HANDLE(NvPhysicalGpuHandle);
00101 NV_DECLARE_HANDLE(NvEventHandle);
00102
00103
00105 #define NVAPI_DEFAULT_HANDLE 0
00106
00109 #define NVAPI_GENERIC_STRING_MAX 4096
00110 #define NVAPI_LONG_STRING_MAX 256
00111 #define NVAPI_SHORT_STRING_MAX 64
00113
00115 typedef struct
00116 {
00117 NvS32 sX;
00118 NvS32 sY;
00119 NvS32 sWidth;
00120 NvS32 sHeight;
00121 } NvSBox;
00122
00125 #define NVAPI_MAX_PHYSICAL_GPUS 64
00126 #define NVAPI_MAX_LOGICAL_GPUS 64
00127 #define NVAPI_MAX_AVAILABLE_GPU_TOPOLOGIES 256
00128 #define NVAPI_MAX_GPU_TOPOLOGIES NVAPI_MAX_PHYSICAL_GPUS
00129 #define NVAPI_MAX_GPU_PER_TOPOLOGY 8
00130 #define NVAPI_MAX_DISPLAY_HEADS 2
00131 #define NVAPI_MAX_DISPLAYS NVAPI_MAX_PHYSICAL_GPUS * NVAPI_MAX_DISPLAY_HEADS
00132
00133 #define NV_MAX_HEADS 4
00134 #define NV_MAX_VID_STREAMS 4
00135 #define NV_MAX_VID_PROFILES 4
00136
00137 typedef char NvAPI_String[NVAPI_GENERIC_STRING_MAX];
00138 typedef char NvAPI_LongString[NVAPI_LONG_STRING_MAX];
00139 typedef char NvAPI_ShortString[NVAPI_SHORT_STRING_MAX];
00141
00142
00143
00148
00149 #define MAKE_NVAPI_VERSION(typeName,ver) (NvU32)(sizeof(typeName) | ((ver)<<16))
00150
00152 #define GET_NVAPI_VERSION(ver) (NvU32)((ver)>>16)
00153
00155 #define GET_NVAPI_SIZE(ver) (NvU32)((ver) & 0xffff)
00156
00157
00158
00162
00163
00164
00165 typedef enum
00166 {
00167 NVAPI_OK = 0,
00168 NVAPI_ERROR = -1,
00169 NVAPI_LIBRARY_NOT_FOUND = -2,
00170 NVAPI_NO_IMPLEMENTATION = -3,
00171 NVAPI_API_NOT_INTIALIZED = -4,
00172 NVAPI_INVALID_ARGUMENT = -5,
00173 NVAPI_NVIDIA_DEVICE_NOT_FOUND = -6,
00174 NVAPI_END_ENUMERATION = -7,
00175 NVAPI_INVALID_HANDLE = -8,
00176 NVAPI_INCOMPATIBLE_STRUCT_VERSION = -9,
00177 NVAPI_HANDLE_INVALIDATED = -10,
00178 NVAPI_OPENGL_CONTEXT_NOT_CURRENT = -11,
00179 NVAPI_NO_GL_EXPERT = -12,
00180 NVAPI_INSTRUMENTATION_DISABLED = -13,
00181 NVAPI_EXPECTED_LOGICAL_GPU_HANDLE = -100,
00182 NVAPI_EXPECTED_PHYSICAL_GPU_HANDLE = -101,
00183 NVAPI_EXPECTED_DISPLAY_HANDLE = -102,
00184 NVAPI_INVALID_COMBINATION = -103,
00185 NVAPI_NOT_SUPPORTED = -104,
00186 NVAPI_PORTID_NOT_FOUND = -105,
00187 NVAPI_EXPECTED_UNATTACHED_DISPLAY_HANDLE = -106,
00188 NVAPI_INVALID_PERF_LEVEL = -107,
00189 NVAPI_DEVICE_BUSY = -108,
00190 NVAPI_NV_PERSIST_FILE_NOT_FOUND = -109,
00191 NVAPI_PERSIST_DATA_NOT_FOUND = -110,
00192 NVAPI_EXPECTED_TV_DISPLAY = -111,
00193 NVAPI_EXPECTED_TV_DISPLAY_ON_DCONNECTOR = -112,
00194 NVAPI_NO_ACTIVE_SLI_TOPOLOGY = -113,
00195 NVAPI_SLI_RENDERING_MODE_NOTALLOWED = -114,
00196 NVAPI_EXPECTED_DIGITAL_FLAT_PANEL = -115,
00197 NVAPI_ARGUMENT_EXCEED_MAX_SIZE = -116,
00198 NVAPI_DEVICE_SWITCHING_NOT_ALLOWED = -117,
00199 NVAPI_TESTING_CLOCKS_NOT_SUPPORTED = -118,
00200 NVAPI_UNKNOWN_UNDERSCAN_CONFIG = -119,
00201 NVAPI_TIMEOUT_RECONFIGURING_GPU_TOPO = -120,
00202 NVAPI_DATA_NOT_FOUND = -121,
00203 NVAPI_EXPECTED_ANALOG_DISPLAY = -122,
00204 NVAPI_NO_VIDLINK = -123,
00205 NVAPI_REQUIRES_REBOOT = -124,
00206 NVAPI_INVALID_HYBRID_MODE = -125,
00207 NVAPI_MIXED_TARGET_TYPES = -126,
00208 NVAPI_SYSWOW64_NOT_SUPPORTED = -127,
00209 NVAPI_IMPLICIT_SET_GPU_TOPOLOGY_CHANGE_NOT_ALLOWED = -128,
00210 NVAPI_REQUEST_USER_TO_CLOSE_NON_MIGRATABLE_APPS = -129,
00211 NVAPI_OUT_OF_MEMORY = -130,
00212 NVAPI_WAS_STILL_DRAWING = -131,
00213 NVAPI_FILE_NOT_FOUND = -132,
00214 NVAPI_TOO_MANY_UNIQUE_STATE_OBJECTS = -133,
00215 NVAPI_INVALID_CALL = -134,
00216 NVAPI_D3D10_1_LIBRARY_NOT_FOUND = -135,
00217 NVAPI_FUNCTION_NOT_FOUND = -136,
00218 } NvAPI_Status;
00219
00221
00222
00223
00238 NVAPI_INTERFACE NvAPI_Initialize();
00239
00241
00242
00243
00257 NVAPI_INTERFACE NvAPI_GetErrorMessage(NvAPI_Status nr,NvAPI_ShortString szDesc);
00258
00260
00261
00262
00278 NVAPI_INTERFACE NvAPI_GetInterfaceVersionString(NvAPI_ShortString szDesc);
00279
00281
00282
00283
00284
00285
00286
00287
00288
00290
00293 typedef struct
00294 {
00295 NvU32 version;
00296 NvU32 drvVersion;
00297 NvU32 bldChangeListNum;
00298 NvAPI_ShortString szBuildBranchString;
00299 NvAPI_ShortString szAdapterString;
00300 } NV_DISPLAY_DRIVER_VERSION;
00301
00303 #define NV_DISPLAY_DRIVER_VERSION_VER MAKE_NVAPI_VERSION(NV_DISPLAY_DRIVER_VERSION,1)
00304
00305
00321 NVAPI_INTERFACE NvAPI_GetDisplayDriverVersion(NvDisplayHandle hNvDisplay, NV_DISPLAY_DRIVER_VERSION *pVersion);
00322
00323
00325
00326
00327
00365 NVAPI_INTERFACE NvAPI_EnumNvidiaDisplayHandle(NvU32 thisEnum, NvDisplayHandle *pNvDispHandle);
00366
00368
00369
00370
00389 NVAPI_INTERFACE NvAPI_EnumNvidiaUnAttachedDisplayHandle(NvU32 thisEnum, NvUnAttachedDisplayHandle *pNvUnAttachedDispHandle);
00390
00392
00393
00394
00420 NVAPI_INTERFACE NvAPI_EnumPhysicalGPUs(NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
00421
00423
00424
00425
00451 NVAPI_INTERFACE NvAPI_EnumLogicalGPUs(NvLogicalGpuHandle nvGPUHandle[NVAPI_MAX_LOGICAL_GPUS], NvU32 *pGpuCount);
00452
00454
00455
00456
00474 NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromDisplay(NvDisplayHandle hNvDisp, NvPhysicalGpuHandle nvGPUHandle[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
00475
00477
00478
00479
00494 NVAPI_INTERFACE NvAPI_GetPhysicalGPUFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvPhysicalGpuHandle *pPhysicalGpu);
00495
00497
00498
00499
00513 NVAPI_INTERFACE NvAPI_CreateDisplayFromUnAttachedDisplay(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvDisplayHandle *pNvDisplay);
00514
00516
00529 NVAPI_INTERFACE NvAPI_GetLogicalGPUFromDisplay(NvDisplayHandle hNvDisp, NvLogicalGpuHandle *pLogicalGPU);
00530
00532
00533
00534
00547 NVAPI_INTERFACE NvAPI_GetLogicalGPUFromPhysicalGPU(NvPhysicalGpuHandle hPhysicalGPU, NvLogicalGpuHandle *pLogicalGPU);
00548
00550
00551
00552
00553
00570 NVAPI_INTERFACE NvAPI_GetPhysicalGPUsFromLogicalGPU(NvLogicalGpuHandle hLogicalGPU,NvPhysicalGpuHandle hPhysicalGPU[NVAPI_MAX_PHYSICAL_GPUS], NvU32 *pGpuCount);
00571
00573
00574
00575
00588 NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayHandle(const char *szDisplayName, NvDisplayHandle *pNvDispHandle);
00589
00590
00592
00593
00594
00606 NVAPI_INTERFACE NvAPI_GetAssociatedNvidiaDisplayName(NvDisplayHandle NvDispHandle, NvAPI_ShortString szDisplayName);
00607
00609
00610
00611
00623 NVAPI_INTERFACE NvAPI_GetUnAttachedAssociatedDisplayName(NvUnAttachedDisplayHandle hNvUnAttachedDisp, NvAPI_ShortString szDisplayName);
00624
00625
00626
00628
00629
00630
00641 NVAPI_INTERFACE NvAPI_EnableHWCursor(NvDisplayHandle hNvDisplay);
00642
00644
00645
00646
00656 NVAPI_INTERFACE NvAPI_DisableHWCursor(NvDisplayHandle hNvDisplay);
00657
00659
00660
00661
00671 NVAPI_INTERFACE NvAPI_GetVBlankCounter(NvDisplayHandle hNvDisplay, NvU32 *pCounter);
00672
00674
00675
00700 NVAPI_INTERFACE NvAPI_SetRefreshRateOverride(NvDisplayHandle hNvDisplay, NvU32 outputsMask, float refreshRate, NvU32 bSetDeferred);
00701
00703
00704
00705
00722 NVAPI_INTERFACE NvAPI_GetAssociatedDisplayOutputId(NvDisplayHandle hNvDisplay, NvU32 *pOutputId);
00723
00725
00726
00727
00728
00729
00730
00731
00732
00733
00734
00735
00736
00737
00739
00740
00743 typedef enum
00744 {
00745 NV_DP_1_62GBPS = 6,
00746 NV_DP_2_70GBPS = 0xA,
00747 } NV_DP_LINK_RATE;
00748
00749
00752 typedef enum
00753 {
00754 NV_DP_1_LANE = 1,
00755 NV_DP_2_LANE = 2,
00756 NV_DP_4_LANE = 4,
00757 } NV_DP_LANE_COUNT;
00758
00759
00762 typedef enum
00763 {
00764 NV_DP_COLOR_FORMAT_RGB = 0,
00765 NV_DP_COLOR_FORMAT_YCbCr422,
00766 NV_DP_COLOR_FORMAT_YCbCr444,
00767 } NV_DP_COLOR_FORMAT;
00768
00769
00772 typedef enum
00773 {
00774 NV_DP_COLORIMETRY_RGB = 0,
00775 NV_DP_COLORIMETRY_YCbCr_ITU601,
00776 NV_DP_COLORIMETRY_YCbCr_ITU709,
00777 } NV_DP_COLORIMETRY;
00778
00779
00782 typedef enum
00783 {
00784 NV_DP_DYNAMIC_RANGE_VESA = 0,
00785 NV_DP_DYNAMIC_RANGE_CEA,
00786 } NV_DP_DYNAMIC_RANGE;
00787
00788
00791 typedef enum
00792 {
00793 NV_DP_BPC_DEFAULT = 0,
00794 NV_DP_BPC_6,
00795 NV_DP_BPC_8,
00796 NV_DP_BPC_10,
00797 NV_DP_BPC_12,
00798 NV_DP_BPC_16,
00799 } NV_DP_BPC;
00800
00801
00804 typedef struct
00805 {
00806 NvU32 version;
00807 NvU32 dpcd_ver;
00808 NV_DP_LINK_RATE maxLinkRate;
00809 NV_DP_LANE_COUNT maxLaneCount;
00810 NV_DP_LINK_RATE curLinkRate;
00811 NV_DP_LANE_COUNT curLaneCount;
00812 NV_DP_COLOR_FORMAT colorFormat;
00813 NV_DP_DYNAMIC_RANGE dynamicRange;
00814 NV_DP_COLORIMETRY colorimetry;
00815 NV_DP_BPC bpc;
00816 NvU32 isDp : 1;
00817 NvU32 isInternalDp : 1;
00818 NvU32 isColorCtrlSupported : 1;
00819 NvU32 is6BPCSupported : 1;
00820 NvU32 is8BPCSupported : 1;
00821 NvU32 is10BPCSupported : 1;
00822 NvU32 is12BPCSupported : 1;
00823 NvU32 is16BPCSupported : 1;
00824
00825 } NV_DISPLAY_PORT_INFO;
00826
00827 #define NV_DISPLAY_PORT_INFO_VER MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_INFO,1)
00828
00829
00830
00847 NVAPI_INTERFACE NvAPI_GetDisplayPortInfo(NvDisplayHandle hNvDisplay, NvU32 outputId, NV_DISPLAY_PORT_INFO *pInfo);
00848
00850
00851
00852
00853
00854
00855
00856
00857
00858
00859
00860
00861
00863
00864
00867 typedef struct
00868 {
00869 NvU32 version;
00870 NV_DP_LINK_RATE linkRate;
00871 NV_DP_LANE_COUNT laneCount;
00872 NV_DP_COLOR_FORMAT colorFormat;
00873 NV_DP_DYNAMIC_RANGE dynamicRange;
00874 NV_DP_COLORIMETRY colorimetry;
00875 NV_DP_BPC bpc;
00876 NvU32 isHPD : 1;
00877 NvU32 isSetDeferred : 1;
00878 NvU32 isChromaLpfOff : 1;
00879 NvU32 isDitherOff : 1;
00880
00881 } NV_DISPLAY_PORT_CONFIG;
00882
00886 #define NV_DISPLAY_PORT_CONFIG_VER MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,2)
00887 #define NV_DISPLAY_PORT_CONFIG_VER_1 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,1)
00888 #define NV_DISPLAY_PORT_CONFIG_VER_2 MAKE_NVAPI_VERSION(NV_DISPLAY_PORT_CONFIG,2)
00890
00891
00893
00911 NVAPI_INTERFACE NvAPI_SetDisplayPort(NvDisplayHandle hNvDisplay, NvU32 outputId, NV_DISPLAY_PORT_CONFIG *pCfg);
00912
00914
00915
00916
00917
00918
00919
00920
00921
00922
00923
00924
00925
00926
00928
00931 typedef struct
00932 {
00933 NvU32 version;
00934 NvU32 isGpuHDMICapable : 1;
00935 NvU32 isMonUnderscanCapable : 1;
00936 NvU32 isMonBasicAudioCapable : 1;
00937 NvU32 isMonYCbCr444Capable : 1;
00938 NvU32 isMonYCbCr422Capable : 1;
00939 NvU32 isMonxvYCC601Capable : 1;
00940 NvU32 isMonxvYCC709Capable : 1;
00941 NvU32 isMonHDMI : 1;
00942 NvU32 EDID861ExtRev;
00943 } NV_HDMI_SUPPORT_INFO;
00944
00945
00947 #define NV_HDMI_SUPPORT_INFO_VER MAKE_NVAPI_VERSION(NV_HDMI_SUPPORT_INFO,1)
00948
00949
00965 NVAPI_INTERFACE NvAPI_GetHDMISupportInfo(NvDisplayHandle hNvDisplay, NvU32 outputId, NV_HDMI_SUPPORT_INFO *pInfo);
00966
00968
00969
00970
00983 NVAPI_INTERFACE NvAPI_GPU_GetAllOutputs(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pOutputsMask);
00984
00986
00987
00988
01002 NVAPI_INTERFACE NvAPI_GPU_GetConnectedOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
01003
01004
01006
01007
01008
01024 NVAPI_INTERFACE NvAPI_GPU_GetConnectedSLIOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
01025
01026
01027
01029
01030
01031
01051 NVAPI_INTERFACE NvAPI_GPU_GetConnectedOutputsWithLidState(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
01052
01053
01055
01056
01057
01073 NVAPI_INTERFACE NvAPI_GPU_GetConnectedSLIOutputsWithLidState(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
01074
01075
01077
01078
01079
01080
01081
01082
01083
01084
01085
01086
01088
01091 typedef enum
01092 {
01093 NV_SYSTEM_TYPE_UNKNOWN = 0,
01094 NV_SYSTEM_TYPE_LAPTOP = 1,
01095 NV_SYSTEM_TYPE_DESKTOP = 2,
01096
01097 } NV_SYSTEM_TYPE;
01098
01099
01112 NVAPI_INTERFACE NvAPI_GPU_GetSystemType(NvPhysicalGpuHandle hPhysicalGpu, NV_SYSTEM_TYPE *pSystemType);
01113
01114
01116
01117
01118
01132 NVAPI_INTERFACE NvAPI_GPU_GetActiveOutputs(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pOutputsMask);
01133
01135
01136
01137
01138
01139
01140
01141
01142
01143
01144
01145
01146
01148
01149
01151 #define NV_EDID_V1_DATA_SIZE 256
01152
01154 #define NV_EDID_DATA_SIZE NV_EDID_V1_DATA_SIZE
01155
01156
01159 typedef struct
01160 {
01161 NvU32 version;
01162 NvU8 EDID_Data[NV_EDID_DATA_SIZE];
01163 NvU32 sizeofEDID;
01164 } NV_EDID;
01165
01167 #define NV_EDID_VER MAKE_NVAPI_VERSION(NV_EDID,2)
01168
01169
01184 NVAPI_INTERFACE NvAPI_GPU_GetEDID(NvPhysicalGpuHandle hPhysicalGpu, NvU32 displayOutputId, NV_EDID *pEDID);
01185
01187
01188
01189
01190
01191
01192
01193
01194
01195
01196
01197
01199
01202 typedef enum _NV_GPU_OUTPUT_TYPE
01203 {
01204 NVAPI_GPU_OUTPUT_UNKNOWN = 0,
01205 NVAPI_GPU_OUTPUT_CRT = 1,
01206 NVAPI_GPU_OUTPUT_DFP = 2,
01207 NVAPI_GPU_OUTPUT_TV = 3,
01208 } NV_GPU_OUTPUT_TYPE;
01209
01210
01211
01212
01225 NVAPI_INTERFACE NvAPI_GPU_GetOutputType(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputId, NV_GPU_OUTPUT_TYPE *pOutputType);
01226
01227
01229
01230
01231
01253 NVAPI_INTERFACE NvAPI_GPU_ValidateOutputCombination(NvPhysicalGpuHandle hPhysicalGpu, NvU32 outputsMask);
01254
01255
01258 typedef enum _NV_GPU_CONNECTOR_TYPE
01259 {
01260 NVAPI_GPU_CONNECTOR_VGA_15_PIN = 0x00000000,
01261 NVAPI_GPU_CONNECTOR_TV_COMPOSITE = 0x00000010,
01262 NVAPI_GPU_CONNECTOR_TV_SVIDEO = 0x00000011,
01263 NVAPI_GPU_CONNECTOR_TV_HDTV_COMPONENT = 0x00000013,
01264 NVAPI_GPU_CONNECTOR_TV_SCART = 0x00000014,
01265 NVAPI_GPU_CONNECTOR_TV_COMPOSITE_SCART_ON_EIAJ4120 = 0x00000016,
01266 NVAPI_GPU_CONNECTOR_TV_HDTV_EIAJ4120 = 0x00000017,
01267 NVAPI_GPU_CONNECTOR_PC_POD_HDTV_YPRPB = 0x00000018,
01268 NVAPI_GPU_CONNECTOR_PC_POD_SVIDEO = 0x00000019,
01269 NVAPI_GPU_CONNECTOR_PC_POD_COMPOSITE = 0x0000001A,
01270 NVAPI_GPU_CONNECTOR_DVI_I_TV_SVIDEO = 0x00000020,
01271 NVAPI_GPU_CONNECTOR_DVI_I_TV_COMPOSITE = 0x00000021,
01272 NVAPI_GPU_CONNECTOR_DVI_I = 0x00000030,
01273 NVAPI_GPU_CONNECTOR_DVI_D = 0x00000031,
01274 NVAPI_GPU_CONNECTOR_ADC = 0x00000032,
01275 NVAPI_GPU_CONNECTOR_LFH_DVI_I_1 = 0x00000038,
01276 NVAPI_GPU_CONNECTOR_LFH_DVI_I_2 = 0x00000039,
01277 NVAPI_GPU_CONNECTOR_SPWG = 0x00000040,
01278 NVAPI_GPU_CONNECTOR_OEM = 0x00000041,
01279 NVAPI_GPU_CONNECTOR_DISPLAYPORT_EXTERNAL = 0x00000046,
01280 NVAPI_GPU_CONNECTOR_DISPLAYPORT_INTERNAL = 0x00000047,
01281 NVAPI_GPU_CONNECTOR_HDMI_A = 0x00000061,
01282 NVAPI_GPU_CONNECTOR_UNKNOWN = 0xFFFFFFFF,
01283 } NV_GPU_CONNECTOR_TYPE;
01284
01286
01287
01288
01298 NVAPI_INTERFACE NvAPI_GPU_GetFullName(NvPhysicalGpuHandle hPhysicalGpu, NvAPI_ShortString szName);
01299
01301
01302
01303
01321 NVAPI_INTERFACE NvAPI_GPU_GetPCIIdentifiers(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pDeviceId,NvU32 *pSubSystemId,NvU32 *pRevisionId,NvU32 *pExtDeviceId);
01322
01323
01324
01327 typedef enum _NV_GPU_TYPE
01328 {
01329 NV_SYSTEM_TYPE_GPU_UNKNOWN = 0,
01330 NV_SYSTEM_TYPE_IGPU = 1,
01331 NV_SYSTEM_TYPE_DGPU = 2,
01332 } NV_GPU_TYPE;
01333
01335
01336
01337
01352 NVAPI_INTERFACE NvAPI_GPU_GetGPUType(NvPhysicalGpuHandle hPhysicalGpu, NV_GPU_TYPE *pGpuType);
01353
01354
01355
01356
01359 typedef enum _NV_GPU_BUS_TYPE
01360 {
01361 NVAPI_GPU_BUS_TYPE_UNDEFINED = 0,
01362 NVAPI_GPU_BUS_TYPE_PCI = 1,
01363 NVAPI_GPU_BUS_TYPE_AGP = 2,
01364 NVAPI_GPU_BUS_TYPE_PCI_EXPRESS = 3,
01365 NVAPI_GPU_BUS_TYPE_FPCI = 4,
01366 } NV_GPU_BUS_TYPE;
01368
01369
01370
01383 NVAPI_INTERFACE NvAPI_GPU_GetBusType(NvPhysicalGpuHandle hPhysicalGpu,NV_GPU_BUS_TYPE *pBusType);
01384
01385
01387
01388
01389
01403 NVAPI_INTERFACE NvAPI_GPU_GetBusId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusId);
01404
01406
01407
01408
01422 NVAPI_INTERFACE NvAPI_GPU_GetBusSlotId(NvPhysicalGpuHandle hPhysicalGpu, NvU32 *pBusSlotId);
01423
01424
01425
01427
01428
01429
01442 NVAPI_INTERFACE NvAPI_GPU_GetIRQ(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pIRQ);
01443
01445
01446
01447
01460 NVAPI_INTERFACE NvAPI_GPU_GetVbiosRevision(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pBiosRevision);
01461
01463
01476 NVAPI_INTERFACE NvAPI_GPU_GetVbiosOEMRevision(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pBiosRevision);
01477
01478
01480
01481
01482
01497 NVAPI_INTERFACE NvAPI_GPU_GetVbiosVersionString(NvPhysicalGpuHandle hPhysicalGpu,NvAPI_ShortString szBiosRevision);
01498
01500
01501
01502
01515 NVAPI_INTERFACE NvAPI_GPU_GetAGPAperture(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
01516
01518
01519
01520
01533 NVAPI_INTERFACE NvAPI_GPU_GetCurrentAGPRate(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pRate);
01534
01536
01537
01538
01552 NVAPI_INTERFACE NvAPI_GPU_GetCurrentPCIEDownstreamWidth(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pWidth);
01553
01554
01555
01557
01558
01559
01573 NVAPI_INTERFACE NvAPI_GPU_GetPhysicalFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
01574
01576
01577
01578
01592 NVAPI_INTERFACE NvAPI_GPU_GetVirtualFrameBufferSize(NvPhysicalGpuHandle hPhysicalGpu,NvU32 *pSize);
01593
01594
01596
01597
01598
01600 #define NVAPI_MAX_THERMAL_SENSORS_PER_GPU 3
01601
01604 typedef enum
01605 {
01606 NVAPI_THERMAL_TARGET_NONE = 0,
01607 NVAPI_THERMAL_TARGET_GPU = 1,
01608 NVAPI_THERMAL_TARGET_MEMORY = 2,
01609 NVAPI_THERMAL_TARGET_POWER_SUPPLY = 4,
01610 NVAPI_THERMAL_TARGET_BOARD = 8,
01611 NVAPI_THERMAL_TARGET_ALL = 15,
01612 NVAPI_THERMAL_TARGET_UNKNOWN = -1,
01613 } NV_THERMAL_TARGET;
01614
01617 typedef enum
01618 {
01619 NVAPI_THERMAL_CONTROLLER_NONE = 0,
01620 NVAPI_THERMAL_CONTROLLER_GPU_INTERNAL,
01621 NVAPI_THERMAL_CONTROLLER_ADM1032,
01622 NVAPI_THERMAL_CONTROLLER_MAX6649,
01623 NVAPI_THERMAL_CONTROLLER_MAX1617,
01624 NVAPI_THERMAL_CONTROLLER_LM99,
01625 NVAPI_THERMAL_CONTROLLER_LM89,
01626 NVAPI_THERMAL_CONTROLLER_LM64,
01627 NVAPI_THERMAL_CONTROLLER_ADT7473,
01628 NVAPI_THERMAL_CONTROLLER_SBMAX6649,
01629 NVAPI_THERMAL_CONTROLLER_VBIOSEVT,
01630 NVAPI_THERMAL_CONTROLLER_OS,
01631 NVAPI_THERMAL_CONTROLLER_UNKNOWN = -1,
01632 } NV_THERMAL_CONTROLLER;
01633
01636 typedef struct
01637 {
01638 NvU32 version;
01639 NvU32 count;
01640 struct
01641 {
01642 NV_THERMAL_CONTROLLER controller;
01643 NvU32 defaultMinTemp;
01644 NvU32 defaultMaxTemp;
01645 NvU32 currentTemp;
01646 NV_THERMAL_TARGET target;
01647 } sensor[NVAPI_MAX_THERMAL_SENSORS_PER_GPU];
01648
01649 } NV_GPU_THERMAL_SETTINGS;
01650
01652 #define NV_GPU_THERMAL_SETTINGS_VER MAKE_NVAPI_VERSION(NV_GPU_THERMAL_SETTINGS,1)
01653
01655
01656
01657
01680 NVAPI_INTERFACE NvAPI_GPU_GetThermalSettings(NvPhysicalGpuHandle hPhysicalGpu, NvU32 sensorIndex, NV_GPU_THERMAL_SETTINGS *pThermalSettings);
01681
01682
01684
01685
01686
01688
01691 typedef enum _NV_DISPLAY_TV_FORMAT
01692 {
01693 NV_DISPLAY_TV_FORMAT_NONE = 0,
01694 NV_DISPLAY_TV_FORMAT_SD_NTSCM = 0x00000001,
01695 NV_DISPLAY_TV_FORMAT_SD_NTSCJ = 0x00000002,
01696 NV_DISPLAY_TV_FORMAT_SD_PALM = 0x00000004,
01697 NV_DISPLAY_TV_FORMAT_SD_PALBDGH = 0x00000008,
01698 NV_DISPLAY_TV_FORMAT_SD_PALN = 0x00000010,
01699 NV_DISPLAY_TV_FORMAT_SD_PALNC = 0x00000020,
01700 NV_DISPLAY_TV_FORMAT_SD_576i = 0x00000100,
01701 NV_DISPLAY_TV_FORMAT_SD_480i = 0x00000200,
01702 NV_DISPLAY_TV_FORMAT_ED_480p = 0x00000400,
01703 NV_DISPLAY_TV_FORMAT_ED_576p = 0x00000800,
01704 NV_DISPLAY_TV_FORMAT_HD_720p = 0x00001000,
01705 NV_DISPLAY_TV_FORMAT_HD_1080i = 0x00002000,
01706 NV_DISPLAY_TV_FORMAT_HD_1080p = 0x00004000,
01707 NV_DISPLAY_TV_FORMAT_HD_720p50 = 0x00008000,
01708 NV_DISPLAY_TV_FORMAT_HD_1080p24 = 0x00010000,
01709 NV_DISPLAY_TV_FORMAT_HD_1080i50 = 0x00020000,
01710 NV_DISPLAY_TV_FORMAT_HD_1080p50 = 0x00040000,
01711
01712 } NV_DISPLAY_TV_FORMAT;
01713
01715
01716
01717
01718
01719
01722 #define NVAPI_MAX_SIZEOF_I2C_DATA_BUFFER 256
01723 #define NVAPI_NO_PORTID_FOUND 5
01724 #define NVAPI_DISPLAY_DEVICE_MASK_MAX 24
01725
01727 typedef struct
01728 {
01729 NvU32 version;
01730 NvU32 displayMask;
01731 NvU8 bIsDDCPort;
01732 NvU8 i2cDevAddress;
01733 NvU8* pbI2cRegAddress;
01734 NvU32 regAddrSize;
01735 NvU8* pbData;
01736 NvU32 cbSize;
01737 NvU32 i2cSpeed;
01738 } NV_I2C_INFO;
01739
01740 #define NV_I2C_INFO_VER MAKE_NVAPI_VERSION(NV_I2C_INFO,1)
01742
01743
01744
01746
01747
01748
01765 NVAPI_INTERFACE NvAPI_I2CRead(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo);
01766
01768
01769
01770
01787 NVAPI_INTERFACE NvAPI_I2CWrite(NvPhysicalGpuHandle hPhysicalGpu, NV_I2C_INFO *pI2cInfo);
01788
01789
01790
01793 typedef struct
01794 {
01795 NvU32 version;
01796 NvU32 vendorId;
01797 NvU32 deviceId;
01798 NvAPI_ShortString szVendorName;
01799 NvAPI_ShortString szChipsetName;
01800 NvU32 flags;
01801 NvU32 subSysVendorId;
01802 NvU32 subSysDeviceId;
01803 NvAPI_ShortString szSubSysVendorName;
01804 } NV_CHIPSET_INFO;
01805
01808 #define NV_CHIPSET_INFO_VER MAKE_NVAPI_VERSION(NV_CHIPSET_INFO,3)
01809
01810
01813 typedef enum
01814 {
01815 NV_CHIPSET_INFO_HYBRID = 0x00000001,
01816 } NV_CHIPSET_INFO_FLAGS;
01817
01818
01821 typedef struct
01822 {
01823 NvU32 version;
01824 NvU32 vendorId;
01825 NvU32 deviceId;
01826 NvAPI_ShortString szVendorName;
01827 NvAPI_ShortString szChipsetName;
01828 NvU32 flags;
01829 } NV_CHIPSET_INFO_v2;
01830
01831
01834 #define NV_CHIPSET_INFO_VER_2 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v2,2)
01835
01836
01839 typedef struct
01840 {
01841 NvU32 version;
01842 NvU32 vendorId;
01843 NvU32 deviceId;
01844 NvAPI_ShortString szVendorName;
01845 NvAPI_ShortString szChipsetName;
01846 } NV_CHIPSET_INFO_v1;
01847
01850 #define NV_CHIPSET_INFO_VER_1 MAKE_NVAPI_VERSION(NV_CHIPSET_INFO_v1,1)
01851
01853
01854
01855
01867 NVAPI_INTERFACE NvAPI_SYS_GetChipSetInfo(NV_CHIPSET_INFO *pChipSetInfo);
01868
01869
01872 typedef struct
01873 {
01874 NvU32 version;
01875 NvU32 currentLidState;
01876 NvU32 currentDockState;
01877 NvU32 currentLidPolicy;
01878 NvU32 currentDockPolicy;
01879 NvU32 forcedLidMechanismPresent;
01880 NvU32 forcedDockMechanismPresent;
01881 }NV_LID_DOCK_PARAMS;
01882
01883
01885 #define NV_LID_DOCK_PARAMS_VER MAKE_NVAPI_VERSION(NV_LID_DOCK_PARAMS,1)
01886
01887
01889
01890
01891
01906 NVAPI_INTERFACE NvAPI_SYS_GetLidAndDockInfo(NV_LID_DOCK_PARAMS *pLidAndDock);
01907
01908
01909
01910
01911
01913
01914
01915
01916
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01950
01951
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01959
01961
01964 #define NVAPI_OGLEXPERT_DETAIL_NONE 0x00000000
01965 #define NVAPI_OGLEXPERT_DETAIL_ERROR 0x00000001
01966 #define NVAPI_OGLEXPERT_DETAIL_SWFALLBACK 0x00000002
01967 #define NVAPI_OGLEXPERT_DETAIL_BASIC_INFO 0x00000004
01968 #define NVAPI_OGLEXPERT_DETAIL_DETAILED_INFO 0x00000008
01969 #define NVAPI_OGLEXPERT_DETAIL_PERFORMANCE_WARNING 0x00000010
01970 #define NVAPI_OGLEXPERT_DETAIL_QUALITY_WARNING 0x00000020
01971 #define NVAPI_OGLEXPERT_DETAIL_USAGE_WARNING 0x00000040
01972 #define NVAPI_OGLEXPERT_DETAIL_ALL 0xFFFFFFFF
01973
01974 #define NVAPI_OGLEXPERT_REPORT_NONE 0x00000000
01975 #define NVAPI_OGLEXPERT_REPORT_ERROR 0x00000001
01976 #define NVAPI_OGLEXPERT_REPORT_SWFALLBACK 0x00000002
01977 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_VERTEX 0x00000004
01978 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_GEOMETRY 0x00000008
01979 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_XFB 0x00000010
01980 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_RASTER 0x00000020
01981 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_FRAGMENT 0x00000040
01982 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_ROP 0x00000080
01983 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_FRAMEBUFFER 0x00000100
01984 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_PIXEL 0x00000200
01985 #define NVAPI_OGLEXPERT_REPORT_PIPELINE_TEXTURE 0x00000400
01986 #define NVAPI_OGLEXPERT_REPORT_OBJECT_BUFFEROBJECT 0x00000800
01987 #define NVAPI_OGLEXPERT_REPORT_OBJECT_TEXTURE 0x00001000
01988 #define NVAPI_OGLEXPERT_REPORT_OBJECT_PROGRAM 0x00002000
01989 #define NVAPI_OGLEXPERT_REPORT_OBJECT_FBO 0x00004000
01990 #define NVAPI_OGLEXPERT_REPORT_FEATURE_SLI 0x00008000
01991 #define NVAPI_OGLEXPERT_REPORT_ALL 0xFFFFFFFF
01992
01993
01994 #define NVAPI_OGLEXPERT_OUTPUT_TO_NONE 0x00000000
01995 #define NVAPI_OGLEXPERT_OUTPUT_TO_CONSOLE 0x00000001
01996 #define NVAPI_OGLEXPERT_OUTPUT_TO_DEBUGGER 0x00000004
01997 #define NVAPI_OGLEXPERT_OUTPUT_TO_CALLBACK 0x00000008
01998 #define NVAPI_OGLEXPERT_OUTPUT_TO_ALL 0xFFFFFFFF
01999
02001
02003
02004
02005
02022 typedef void (* NVAPI_OGLEXPERT_CALLBACK) (unsigned int categoryId, unsigned int messageId, unsigned int detailLevel, int objectId, const char *messageStr);
02023
02024
02025
02026
02028
02029
02030
02031
02032
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02075
02076
02078
02080 NVAPI_INTERFACE NvAPI_OGL_ExpertModeSet(NvU32 expertDetailLevel,
02081 NvU32 expertReportMask,
02082 NvU32 expertOutputMask,
02083 NVAPI_OGLEXPERT_CALLBACK expertCallback);
02084
02086 NVAPI_INTERFACE NvAPI_OGL_ExpertModeGet(NvU32 *pExpertDetailLevel,
02087 NvU32 *pExpertReportMask,
02088 NvU32 *pExpertOutputMask,
02089 NVAPI_OGLEXPERT_CALLBACK *pExpertCallback);
02090
02092
02094
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02099
02100
02101
02102
02103
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02105
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02122
02124
02126 NVAPI_INTERFACE NvAPI_OGL_ExpertModeDefaultsSet(NvU32 expertDetailLevel,
02127 NvU32 expertReportMask,
02128 NvU32 expertOutputMask);
02129
02131 NVAPI_INTERFACE NvAPI_OGL_ExpertModeDefaultsGet(NvU32 *pExpertDetailLevel,
02132 NvU32 *pExpertReportMask,
02133 NvU32 *pExpertOutputMask);
02135
02136 #define NVAPI_MAX_VIEW_TARGET 2
02137
02140 typedef enum _NV_TARGET_VIEW_MODE
02141 {
02142 NV_VIEW_MODE_STANDARD = 0,
02143 NV_VIEW_MODE_CLONE = 1,
02144 NV_VIEW_MODE_HSPAN = 2,
02145 NV_VIEW_MODE_VSPAN = 3,
02146 NV_VIEW_MODE_DUALVIEW = 4,
02147 NV_VIEW_MODE_MULTIVIEW = 5,
02148 } NV_TARGET_VIEW_MODE;
02149
02150
02151
02152
02153
02156 typedef enum _NV_SCALING
02157 {
02158 NV_SCALING_DEFAULT = 0,
02159 NV_SCALING_MONITOR_SCALING = 1,
02160 NV_SCALING_ADAPTER_SCALING = 2,
02161 NV_SCALING_CENTERED = 3,
02162 NV_SCALING_ASPECT_SCALING = 5,
02163 NV_SCALING_CUSTOMIZED = 255
02164 } NV_SCALING;
02165
02168 typedef enum _NV_ROTATE
02169 {
02170 NV_ROTATE_0 = 0,
02171 NV_ROTATE_90 = 1,
02172 NV_ROTATE_180 = 2,
02173 NV_ROTATE_270 = 3
02174 } NV_ROTATE;
02175
02178 typedef enum _NV_FORMAT
02179 {
02180 NV_FORMAT_UNKNOWN = 0,
02181 NV_FORMAT_P8 = 41,
02182 NV_FORMAT_R5G6B5 = 23,
02183 NV_FORMAT_A8R8G8B8 = 21,
02184 NV_FORMAT_A16B16G16R16F = 113
02185 } NV_FORMAT;
02186
02187
02188
02189
02191
02192
02193
02195
02198 typedef struct
02199 {
02200 NvU32 version;
02201 NvU32 count;
02202 struct
02203 {
02204 NvU32 deviceMask;
02205 NvU32 sourceId;
02206 NvU32 bPrimary:1;
02207
02208 NvU32 bInterlaced:1;
02209 NvU32 bGDIPrimary:1;
02210 } target[NVAPI_MAX_VIEW_TARGET];
02211 } NV_VIEW_TARGET_INFO;
02212
02214 #define NV_VIEW_TARGET_INFO_VER MAKE_NVAPI_VERSION(NV_VIEW_TARGET_INFO,2)
02215
02216
02236 NVAPI_INTERFACE NvAPI_SetView(NvDisplayHandle hNvDisplay, NV_VIEW_TARGET_INFO *pTargetInfo, NV_TARGET_VIEW_MODE targetView);
02237
02239
02240
02259 NVAPI_INTERFACE NvAPI_GetView(NvDisplayHandle hNvDisplay, NV_VIEW_TARGET_INFO *pTargets, NvU32 *pTargetMaskCount, NV_TARGET_VIEW_MODE *pTargetView);
02260
02262
02263
02264
02266
02268 #define NVAPI_MAX_DISPLAY_PATH NVAPI_MAX_VIEW_TARGET
02269
02270
02273 typedef struct
02274 {
02275 NvU32 version;
02276 NvU32 count;
02277 struct
02278 {
02279 NvU32 deviceMask;
02280 NvU32 sourceId;
02281 NvU32 bPrimary:1;
02282
02283 NV_GPU_CONNECTOR_TYPE connector;
02284
02285
02286 NvU32 width;
02287 NvU32 height;
02288 NvU32 depth;
02289 NV_FORMAT colorFormat;
02290
02291
02292 NV_ROTATE rotation;
02293
02294
02295 NV_SCALING scaling;
02296
02297
02298 NvU32 refreshRate;
02299 NvU32 interlaced:1;
02300
02301 NV_DISPLAY_TV_FORMAT tvFormat;
02302
02303
02304 NvU32 posx;
02305 NvU32 posy;
02306 NvU32 bGDIPrimary:1;
02307 } path[NVAPI_MAX_DISPLAY_PATH];
02308 } NV_DISPLAY_PATH_INFO;
02309
02311 #define NV_DISPLAY_PATH_INFO_VER MAKE_NVAPI_VERSION(NV_DISPLAY_PATH_INFO,2)
02312
02313
02314
02335 NVAPI_INTERFACE NvAPI_SetViewEx(NvDisplayHandle hNvDisplay, NV_DISPLAY_PATH_INFO *pPathInfo, NV_TARGET_VIEW_MODE displayView);
02336
02338
02339
02360 NVAPI_INTERFACE NvAPI_GetViewEx(NvDisplayHandle hNvDisplay, NV_DISPLAY_PATH_INFO *pPathInfo, NvU32 *pPathCount, NV_TARGET_VIEW_MODE *pTargetViewMode);
02361
02363
02364
02381 NVAPI_INTERFACE NvAPI_GetSupportedViews(NvDisplayHandle hNvDisplay, NV_TARGET_VIEW_MODE *pTargetViews, NvU32 *pViewCount);
02382
02383
02384
02385
02386
02387 #ifdef __cplusplus
02388 };
02389 #endif
02390
02391 #pragma pack(pop)
02392
02393 #endif // _NVAPI_H