SLI Zone
NVIDIA.com Developer Home

NVAPI Reference: structNV__DISPLAY__PORT__INFO

NV_DISPLAY_PORT_INFO Struct Reference
[Display Control API Defines, Structs, Enums]

#include <nvapi.h>


Data Fields

NvU32 version
NvU32 dpcd_ver
NV_DP_LINK_RATE maxLinkRate
NV_DP_LANE_COUNT maxLaneCount
NV_DP_LINK_RATE curLinkRate
NV_DP_LANE_COUNT curLaneCount
NV_DP_COLOR_FORMAT colorFormat
NV_DP_DYNAMIC_RANGE dynamicRange
NV_DP_COLORIMETRY colorimetry
NV_DP_BPC bpc
NvU32 isDp: 1
NvU32 isInternalDp: 1
NvU32 isColorCtrlSupported: 1
NvU32 is6BPCSupported: 1
NvU32 is8BPCSupported: 1
NvU32 is10BPCSupported: 1
NvU32 is12BPCSupported: 1
NvU32 is16BPCSupported: 1

Detailed Description

Used in NvAPI_GetDisplayPortInfo().

Field Documentation

NvU32 NV_DISPLAY_PORT_INFO::version

Structure version.

NvU32 NV_DISPLAY_PORT_INFO::dpcd_ver

DPCD version of the monitor.

NV_DP_LINK_RATE NV_DISPLAY_PORT_INFO::maxLinkRate

Maximum supported link rate.

NV_DP_LANE_COUNT NV_DISPLAY_PORT_INFO::maxLaneCount

Maximum supported lane count.

NV_DP_LINK_RATE NV_DISPLAY_PORT_INFO::curLinkRate

Current link rate.

NV_DP_LANE_COUNT NV_DISPLAY_PORT_INFO::curLaneCount

Current lane count.

NV_DP_COLOR_FORMAT NV_DISPLAY_PORT_INFO::colorFormat

Current color format.

NV_DP_DYNAMIC_RANGE NV_DISPLAY_PORT_INFO::dynamicRange

Dynamic range.

NV_DP_COLORIMETRY NV_DISPLAY_PORT_INFO::colorimetry

Ignored in RGB space.

NV_DP_BPC NV_DISPLAY_PORT_INFO::bpc

Current bit-per-component;.

NvU32 NV_DISPLAY_PORT_INFO::isDp

If the monitor is driven by a DisplayPort.

NvU32 NV_DISPLAY_PORT_INFO::isInternalDp

If the monitor is driven by an NV Dp transmitter.

NvU32 NV_DISPLAY_PORT_INFO::isColorCtrlSupported

If the color format change is supported.

NvU32 NV_DISPLAY_PORT_INFO::is6BPCSupported

If 6 bpc is supported.

NvU32 NV_DISPLAY_PORT_INFO::is8BPCSupported

If 8 bpc is supported.

NvU32 NV_DISPLAY_PORT_INFO::is10BPCSupported

If 10 bpc is supported.

NvU32 NV_DISPLAY_PORT_INFO::is12BPCSupported

If 12 bpc is supported.

NvU32 NV_DISPLAY_PORT_INFO::is16BPCSupported

If 16 bpc is supported.

The documentation for this struct was generated from the following file:

Copyright (c) 2007, 2008 NVIDIA Corporation. All rights reserved.